This invention relates to semiconductor devices and methods of making such devices, and more particularly to a dynamic random access memory cell array and a process for manufacturing this array.
Dynamic RAM cells in which both the capacitor and the transistor are located within a trench in the face of a silicon bar are disclosed in my above-mentioned application, and by Richardson, et al, in Proceedings of the International Electronic Devices Meeting, IEEE, 1985, pp. 714-717; these structures greatly reduce the space occupied on the face of the bar, and so the density of cells can be very high. The Richardson, et al cell requires the use of a buried lateral contact to connect the source of the access transistor to the upper plate of the capacitor which forms the storage node, and the manufacturing steps for forming this contact are complex. Cells have been proposed such as that in U.S. Pat. No. 4,225,945 issued to Kuo and assigned to Texas Instruments, in which the capacitor and transistor are located within a trench, and in which the lower capacitor plate is the storage node, so the edge of the capacitor region forms the source of the access transistor and no buried contact is needed.
It is the principal object of this invention to provide an improved dynamic memory cell of the type having both the capacitor and the access transistor located within a trench to thereby reduce the space used on the surface. It is another object to provide a trench-type dynamic memory cell array which is more easily manufactured with existing process technology, particularly one that does not require a buried lateral contact. It is a further object to provide a cell with improved alpha particle immunity, and to provide a cell of smaller size, allowing a greater cell density.